This invention relates to integrated circuits, and more particularly, to configurable circuitry that may be used to implement adders.
Adders are used to perform binary addition in digital integrated circuits. For example, a five bit adder may be used to compute a binary sum of two five bit binary inputs.
Adders are widely used on integrated circuits such as programmable logic devices. Programmable logic device integrated circuits contain programmable logic that may be programmed to implement a desired custom logic design. In some device architectures, programmable logic is organized in regions. Each logic region may contain configurable adder circuits. When a logic designer desires to implement an adder that is larger than an individual adder circuit, the circuitry on the programmable logic device can be selectively configured to combine multiple adder circuits.
Programmable logic device integrated circuits may also contain redundant circuitry. Redundant circuitry may be used to repair a programmable logic device that contains a defect. Fuses may be used to control redundancy multiplexers. When a defective circuit is identified during manufacturing, the fuses may be used to configure the redundancy multiplexers so that the redundant circuitry is switched into use in place of the defective circuits.
Adders produce carry signals. When forming relatively large adders from smaller adder circuits, the carry signals from the smaller adder circuits must be routed appropriately. In programmable logic device integrated circuits with redundant circuitry, redundancy multiplexers are used to form part of the carry signal paths between adders. The redundancy multiplexers are used to route the carry signals appropriately when a defective portion of circuitry is being bypassed.
However, in programmable logic device integrated circuits arrangements in which redundancy multiplexers are used to form adder carry chains, the presence of the redundancy multiplexer circuitry can introduce undesirable carry propagation delays. These delays can limit adder performance, regardless of whether a particular device contains a circuit defect.
It would be desirable to be able to provide improved adder circuitry for integrated circuits such as programmable integrated circuits with redundancy circuitry.